7nm Processor

CPUs are made from billions of small transistors, electrical gates that switch on and off to perform calculations. They take power to do this, and also the smaller the transistor uses the less power is required.

Importance of new process

Moore’s law states that the quantity of transistors on a chip doubles per annum. Back within the late 90s and early 2000s, transistors were decreased in size by half every two years, resulting in massive improvements. Shrinking has gotten more complicated, and that we haven’t seen a transistor shrink from Intel since 2014.

With Intel lagging, even mobile devices have had an opportunity to catch up, with apple’s A12 bionic being manufactured on TSMC’s 7nm process, and Samsung has its own 10nm process

What does “nm” mean?

CPUs are made using Photolithography, where an image of the CPU is etched onto a piece of silicon. The precise method of photolithography done is usually stated as the process node and is measured by how small the manufacturer can make the transistors. we are able to achieve the greater performance of the CPU by using small transistors as they have less power consumption than the prevailing transistor without getting hot. It also allows for smaller die sizes, reducing costs and increasing density at the identical sizes, which implies more cores per chip.

History of 7nm Processor

7 nm scale MOSFET’S were first demonstrated by researchers within the early 2000s. In 2002, an IBM research team fabricated a 6 nm silicon-on-insulator (SOI) MOSFET. In 2003, NEC’S research team fabricated a 5nm MOSFET. In July 2015, IBM announced that that they had built the primary functional transistors with 7 nm technology, employing a silicon-germanium process. In June 2016, TSMC had produced 256 Mbit SRAM memory cells at their 7 nm process with a cell area of 0.027 square micrometers (550 F2 ) with reasonable risk production yields.

What is 7nm?

1. 7nm refers to a technology node that’s one of the most advanced FinFET process nodes utilized in chip design & fabrication
2. 7nm is one of the most recent process nodes in production today that has shrink-down transistors, offering improvement in silicon area utilization and power efficiency, which goes on into production mode for the last couple of months.
3. The tradeoff is an increase in chip design & manufacturing process complexity, together with higher manufacturing/fabrication costs.

Benefits of 7nm process

• The main benefits are PPA i.e., power, performance, and area, which is the main criteria of the Mobile, handheld device, and processor industry.
• Reduced power consumption -This is a key parameter for the mobile/handheld industry, for which power consumption & battery life plays a major role. Per published data, the 7nm TSMC process gives 40% power saving over 10nm.
• Improvement in switching performance — This is equally important in server applications and smartphones, which use faster processors and want to add more threads to their multi-tasking capabilities. Faster switching means faster application run time. Per the info published by TSMC, this shows a 20% speed improvement.
• 1.6x higher density — This is a key advantage to provide the lightest and thinnest possible smartphones. Per published data, TSMC 7nm has resulted in area saving due to 1.6X logic density vis-a-vis 10nm.

Challenges of 7nm Technology

• At the 7nm point, the transistors are placed close to each other that after you try to shrink further (5nm &3nm) an effect called quantum tunneling will come into the picture. because of this effect, the transistor can’t be turned off reliably and for the most part, will remain. . This necessitates close monitoring of the manufacturing process and also the process curve.
• Die Manufacturing -Fabricating transistors is one process, generally called the front-end-of- line (FEOL) process. The back-end-of-line process is employed for all the interconnections, which brings the complex a part of managing resistance-capacitance. There are local interconnects at the device level, accomplished by the middle-of-line process. Global interconnects are done by the back-end of the line and are prone to resistance-capacitance delays. Normally, at lower nodes, the back-end-of-line uses multiple patterning, which calls for extra deposition and etching with every pattern, thus increasing the value of production.
• Logically, multiple patterning can still be used for 7nm. However, the industry is heading toward extreme ultraviolet (EUV) lithography for lower technology nodes. With EUV, the back-end-of-line process can be done with single exposure and throughput can be as good as ~1,000 wafers per day.
• Generally, all semiconductor wafers within the current zone are using photolithography for patterning, supported by a lightweight source with a wavelength of 193nm. Manufacturing processes have relied on pattern features down to one-twentieth of the free-space wavelength of light, including immersion lithography, optical phase control, exotic photochemistry, and multiple patterning. it’s time to switch to a new light source of 13.5nm wavelength, which is the so-called EUV. However, changing to this new wavelength and new processing technology and procedures reveal new challenges for designers. There are changes to the set of DFM rules given by the foundry, to be followed by designers, to ensure their design can be manufactured.

Note:- Within two to five years of span the 2nm chip would take over 7nm and other chips

IBM currently developed a 2nm chip.

Name:-Harsh Jayhar Bhutada

Email:-hbhutada95@gmail.com